1. Field of the Invention
The present invention relates to a semiconductor device with a reduced surface field strength type MOS transistor, a method of manufacturing the same semiconductor device, and a semiconductor device with a load driving semiconductor element such as an LDMOS (Lateral Diffused MOS) transistor (which will be referred hereinafter to as an LDMOS).
2. Description of the Prior Art
As an N-channel LDMOS there has been known an element with a structure as shown in FIG. 14. As illustrated, this LDMOS has an N-type substrate 1, an N well 2 deposited on the N-type substrate 1, a channel P well 3 formed in the N well 2, an N-type diffused layer 4 formed in the channel P well 3 and a different N-type diffused layer 5 provided in the said N well 2. In addition, a gate electrode 7 is located on a substrate surface in a state that a gate oxide film 6 is interposed therebetween while a channel region 8 is formed in a surface area of the channel P well 3 right under the gate electrode 7. In this structure, the N-type diffused layer 4 servers as a source region, the N-type diffused layer 5 acts as a drain region, and the N well 2 under an LOCOS oxide film 9 functions as a drift region. In the illustration, numerals 10 and 11 represent a source electrode and a drain electrode, respectively, numeral 12 designates a diffused layer for taking the electric potential of the channel P well 3, and numeral 13 denotes an inter-layer insulating film.
In the case of such an LDMOS, if the concentration of the N well 2 is heightened in order to reduce the ON resistance to facilitate the current flow, difficulty is encountered to enlarge the depletion layer in the drift region, so that a high breakdown voltage (characteristic bearing a high voltage) becomes unobtainable. On the contrary, if the concentration of the N well 2 falls, although the breakdown voltage improves, the current becomes hard to flow so that the ON resistance increases.
One possible solution of such problems is exemplified by Japanese Patent publication No. 59-24550 and Japanese Unexamined Patent Publication No. 5-267652. The outline of the structure disclosed in these publications is that, as shown in FIG. 15, an N well 2 is formed on a P-type substrate 14. In this case, if the formation of the N well 2 is based on the diffusion, the N well 2 surface shows a high concentration, and hence the flow of the current becomes easy in the N well 2 surface, besides the depletion layer can readily enlarge in the whole N well 2, with the result that a high breakdown voltage is attainable. This LDMOS is called a reduced surface field strength type (RESURF=REduced SURface Field) LDMOS where the dopant concentration in the drift region of the N well 2 is determined to satisfy the so-called RESURF condition as described in the above-mentioned publications.
In the aforesaid reduced surface field strength type LDMOS, the drain electrode 11 and the P-type substrate 14 are in an electrically connected relation to each other, and hence, in cases where as shown in FIG. 16 an L load such as a coil 15 is electrically coupled to the drain electrode 11 so that the L load gets into a driven condition, when the voltage applied to the gate electrode 7 comes into the OFF condition, a reverse voltage of the L load 15 has an influence on the drain electrode 11. This reverse voltage can frequently assume an extremely high value. In this case, since the above-mentioned reduced surface field strength type LDMOS does not take into consideration the current escaping path coping with the reverse voltage, the PN junction between the channel P well 3 and the N well 2 comes into breakdown at the application of the reverse voltage to cause a current to flow from the channel P well 3 through a P.sup.+ diffused layer 12 to the source electrode 10 so that the electric potential of the channel P well 3 exceeds the electric potential of the N-type diffused layer 4, with the result that a parasitic (incidental) transistor comprising the N-type diffused layer 4 acting as the emitter, the channel P well 3 serving as the base and the N well 2 functioning as the collector comes into operation to cause a large current to flow through a narrow area in an arrow direction. Because of the occurrence of the large current passing through the narrow area, the elements are easy to heat so that the breakdown of the elements takes place irrespective of a low reverse voltage, thus resulting in impairing the breakdown proof of the elements.
Furthermore, the aforesaid reduced surface field strength type LDMOS is situated on the P-type substrate 14, and hence, in the case that a V-NPN transistor (which will be referred hereinafter to as an NPNTr) superior in current characteristic to a PNP transistor and the aforesaid reduced surface field strength type LDMOS are formed on the same substrate, since an N layer serving as a collector layer in the NPNTr is made to take a deep position, difficulty is actually experienced to form both the transistors on the same substrate. In this case, although, if having the structure as shown in FIG. 14, the LDMOS, together with the NPNTr, can be formed on the same substrate, the compatibility of a high breakdown voltage and a low ON resistance as described before become impossible.
Moreover, there have been proposed various SOI (Silicon On Insulator) structures in which an element area in one main surface side of a semiconductor substrate is divided and separated using an insulating film such as SiO.sub.2 to form islands. In this case, elements such as a bipolar transistor and CMOS are formed in the island-like divisions, respectively. The aforesaid power LDMOS is considered to be also formed in the island-like element division. For example, in the case that the LDMOS as shown in FIG. 14 is surrounded by an insulating film, the N-type substrate 1 comes into contact with the insulating film. With this structure, the N-type substrate 1 and the N well 2 becomes common in electric potential to its drain. For this reason, in cases where as shown in FIG. 10A a load is driven by a low side switch type where the load is connected to the power supply side and the LDMOS is coupled to the GND side, in response to the switching of the LDMOS, the drain electric potential varies from the potential of the GND to the potential of the power supply (or more), and the potential of the N-type substrate 1 varies accordingly.
In cases where the element separation is made through the use of the insulating film, since there exists a parasitic capacitor, when the electric potential in the region brought into contact with the insulating film greatly varies, switching noises are propagated up to the other element regions so that the other semiconductor elements can get into malfunction. In the case of the reduced surface field strength type LDMOS as shown in FIG. 15, the P-type substrate 14 comes into contact with the separation insulating film. As illustrated, in order to make the P-type substrate 14 and the source electrode equal in electric potential to each other, the formation of a deep P.sup.+ diffused layer for taking the electric potential is necessary. However, in the case that the load is driven by a high side switch type in which as shown in FIG. 10B the LDMOS is connected to the power supply side and the load is coupled to the GND side, in response to the switching of the LDMOS, the source electric potential greatly varies, which can also cause the switching noises.
If, in the SOI structure, elements such as a bipolar transistor and a CMOS of relatively small sizes are formed in the element regions, the aforesaid switching noises does not create a problem. However, in the case of the load driving element such as the LDMOS, the element size increase, thus creating such a problem.